The Technology
Compute hardware built for the era beyond silicon
What It Is
The Photonic Accelerator Unit (PAU) uses photons to perform computations. The shift in compute substrate — from electrons in silicon to light — sidesteps the thermal, power, and supply-chain constraints that conventional accelerators are now hitting.
Why Now
Two independent trends are converging on the same constraint. Per-accelerator power is climbing generation over generation; the electricity available for global AI compute is finite. When the demand curve crosses the substation-and-cooling ceiling, silicon compute stops scaling — regardless of foundry roadmap.
Each accelerator generation extracts more compute per chip by consuming more electricity. A trajectory bounded by substation and cooling capacity, not silicon area. Sources: NVIDIA data-center product specifications
Data-centre electricity share grew from ~1% to ~1.5% of global consumption between 2020 and 2024; the IEA projects it will reach ~3% by 2030 — roughly 12%/year growth, driven primarily by AI inference. Photonic compute directly addresses the joules-per-inference axis this curve is bound by. Source: IEA, Energy and AI (2026)
Why It Matters
Compute-intensive workloads are now bound by physics. Power and heat are no longer engineering details — they dominate the economics of large-scale compute deployments.
A photonic substrate addresses these constraints at the foundation, rather than as an optimisation layered on top of an electronic system.
Absolute demand: global data-centre electricity was about 415 TWh in 2024 and the IEA projects it to more than double to around 945 TWh by 2030. That rising power-and-cost wall is the constraint a photonic substrate is designed to address. Source: IEA, Energy and AI (2026)
Design Principles
Compute happens in the photonic domain. The substrate is engineered for the operating regime PAU requires.
PAU is a general-purpose photonic compute platform. Use cases span AI inference, scientific compute, signal processing, and other workloads where the limits of silicon hardware are the bottleneck.
The fabrication path sits outside the leading-node silicon foundry bottleneck. All components are sourced from suppliers in the United States and Europe. No critical component depends on Asian suppliers.
The architecture is the subject of a US provisional patent application filed at the USPTO in April 2026 (sole inventor). Conversion to a non-provisional filing within the statutory twelve-month priority window is planned, in coordination with patent counsel.
Programme Timeline
A staged development path, gate by gate. Past milestones are dated; future milestones are described by the gate they clear, not by a promised date.
What the Validation Shows
The claims on this page come out of a 2026 software validation campaign that simulates the substrate physics, the per-element arithmetic, and the full inference pipeline on representative workloads. The results below are what that campaign measured — the graphs correspond to the Software validation milestone above.
The specific mechanisms by which these results emerge are the subject of the pending US patent (provisional filed April 2026; non-provisional conversion planned within the statutory window). A future bench prototype will validate the substrate-level claims directly.
Roughly a 50% reduction in elementary operations on multiplication-dominated inference at matched precision. Deliberately shown as a shape, not exact figures.
Every measurement dimension the campaign tested favors the representation our architecture uses. The specific mechanism is reserved to the patent surface.
The Precision Question
The conventional criticism of photonic compute — that it cannot match the numerical precision of digital silicon on demanding inference workloads — applies specifically to continuous-amplitude analog photonic architectures, where the achievable precision is bounded by the analog noise floor of the substrate.
Our architectural approach addresses inference accuracy not through analog-precision improvement, but through compositional mechanisms at the representation and algorithm layers. Software validation of the resulting system reaches floating-point parity within seed-noise on a representative inference workload at the canonical configuration. A future bench prototype build will validate the substrate-level claims directly.
The specific architectural mechanisms by which the system recovers effective accuracy are the subject of the pending US patent and the planned non-provisional conversion.
Research Programmes
Akashion's development runs on a proprietary, in-house approach — from how the architecture is designed to how every claim is checked before it reaches hardware. Two programmes carry that work forward.
A multi-year research programme to build a frontier-class AI system that runs natively on the PAU substrate — not silicon software ported onto photonics, but models and algorithms designed from the ground up for the way PAU computes. PAU-Omega is where the substrate's native parallelism is turned into capability.
Beneath PAU-Omega sits a proprietary computational-design and measurement foundation — the tooling, conventions, and validation campaign that let us prove architectural claims in software before committing them to a bench prototype. This is the layer that keeps the rest of the work reproducible and auditable.
Modelled Projections
Beyond the measured software results above, the substrate physics and per-element arithmetic support modelled projections for deployment-scale speed, wall power, and operating energy cost. These are modelled — derived from substrate-component datasheets and per-element arithmetic counts against a stated conventional baseline — not yet measured. The bench prototype will measure the per-multiply-accumulate energy directly.
Per-device throughput on language workloads. A modelled per-device advantage over a current top-tier inference GPU. The specific multiplier is a modelled projection and is held for publication-gate review before it goes public.
Cluster wall power and annual energy cost. A modelled reduction in total wall power and annual operating energy cost to serve the same fixed workload, against a published-figure conventional baseline. Held for the same reason — modelled multiplier, reserved.
Deployment Model
PAU is designed to deploy alongside existing inference infrastructure rather than in place of it. First-generation units are designed to operate as drop-in additions to existing racks, extending inference capacity without requiring write-off of previously procured equipment.
Subsequent generations follow a phased upgrade path: as new compute capacity is added, photonic units progressively displace traditional equipment until the site reaches a fully photonic configuration. Operators who adopt early are positioned to make that transition incrementally, rather than as a capital-write-off event.